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? semiconductor msm7541/7542 1/20 ? semiconductor msm7541/7542 single rail codec general description the msm7541 and MSM7542 are single-channel codec cmos ics for voice signals ranging from 300 to 3400 hz. these devices contain filters for a/d and d/a conversion. designed especially for a single-power supply and low-power applications, these devices are optimized for telephone terminals in digital wireless systems. the msm7541 and MSM7542 use newly designed operational amplifiers to maintain small current deviations caused by power voltage fluctuations. the devices use the same transmission clocks as those used in the msm7508b and msm7509b. the analog output signal, which is of a differential type, directly drives a piezoelectric type handset receiver. features ? single power supply: +3.0 v to +3.8 v ? low power consumption operating mode: 23 mw typ. v dd = 3.3 v power save mode: 1 mw typ. v dd = 3.3 v power down mode: 0.04 mw typ. v dd = 3.3 v ? itu-t companding law msm7541: m -law MSM7542: a-law ? built-in pll eliminates a master clock ? serial data rate: 64/128/256/512/1024/2048 khz 96/192/384/768/1536/1544/200 khz ? adjustable transmit gain ? adjustable receive gain ? built-in reference voltage supply ? built-in analog loop back test mode ? differential type analog output. directly drives a piezoelectric type receiver equivalent to 1.2 k w + 55 nf ? package options: 20-pin plastic skinny dip (dip20-p-300-2.54-s1) (product name : msm7541rs) (product name : MSM7542rs) 24-pin plastic sop (sop24-p-430-1.27-k) (product name : msm7541gs-k) (product name : MSM7542gs-k) 26-pin plastic tsop (tsopii26/20-p-300-1.27-k) (product name : msm7541ts-k) (product name : MSM7542ts-k) e2u0014-28-81 this version: aug. 1998 previous version: nov. 1996
? semiconductor msm7541/7542 2/20 block diagram rc active bpf (8th) ad conv. transmit controller auto zero lpf (5th) da conv. pwd logic pll rCtim receive controller pcmout xsync bclock rsync pcmin pdn v dd ag dg signal ground sgc sg sg voltage ref. power down + C ain+ ainC gsx tmc C + vfro sg sg C + aout+ sg C + aoutC sg pwi
? semiconductor msm7541/7542 3/20 pin configuration (top view) nc : no connect pin nc : no connect pin nc : no connect pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sg aout+ aoutC pwi vfro v dd dg pdn sgc ain+ ainC gsx tmc ag bclock rsync pcmin xsync pcmout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 sg aout+ aoutC pwi vfro v dd dg pdn sgc ain+ ainC gsx tmc ag bclock rsync pcmin xsync pcmout 1 2 3 4 5 9 10 11 12 13 14 15 16 17 18 22 23 24 25 26 sg aout+ aoutC pwi vfro v dd dg pdn sgc ain+ ainC gsx ag bclock rsync pcmin xsync pcmout tmc nc nc nc nc nc nc nc 24-pin plastic sop 20-pin plastic skinn y dip 26-pin plastic tsop
? semiconductor msm7541/7542 4/20 pin and functional descriptions ain+, ainC, gsx transmit analog input and transmit level adjustment. ain+ is a non-inverting input to the op-amp; ainC is an inverting input to the op-amp; gsx is connected to the output of the op-amp and is used to adjust the level, as shown below. when not using ainC and ain+, connect ainC to gsx and ain+ to sg. during power saving and power down modes, the gsx output is at ag voltage. ag analog signal ground. vfro receive filter output. the output signal has an amplitude of 2.0 v pp above and below the signal ground voltage (sg) when the digital signal of +3 dbmo is input to pcmin and can drive a load of 20 k w or more. for driving a load of 20 k w or less, the output signal of aout+ and aoutC is available. to apply the output signal of aout+ and aoutC for driving, connect a resistor of 20 k w or more between the pins vfro and pwi. when adding the frequency characteristics to the receive signal, refer to the application example. during power saving or power down mode, the output of vfro is at the voltage level of ag. C + ainC ain+ c1 analog input 1) inverting input type r1 : variable r2 > 20 k w c1 > 1/(2 3.14 30 r1) gain = r2/r1 10 r2 gsx sg + C ain+ ainC 2) non inverting input type r3 > 20 k w r4 > 20 k w r5 > 50 k w c2 > 1/ (2 3.14 30 r5) gain = 1 + r4 / r3 10 r4 gsx sg c2 analog input r3 r5 r1
? semiconductor msm7541/7542 5/20 pwi, aout+, aoutC pwi is connected to the inverting input of the receive driver. the receive driver output is connected to the aoutC pin. therefore, the receive level can be adjusted with the pins vfro, pwi, and aoutC. when the pwi pin is not used, connect the pwi pin to the aoutC pin, and leave open the pins aoutC and aout+. the output of aout+ is inverted with respect to the output of aoutC. since the signal from which provides differential drives of an impedance of 1.2 k w + 55 nf, these outputs can directly be connected to a receiver of handset using a piezoelectric earphone. refer to the application example. r6 > 20 k w zl 3 2.4 k w gain = vo/vi = 2 r7/r6 2 r6 r7 C + sg C + sg vfro pwi aoutC aout+ receive filter zl vo vi during power saving and power down modes, the outputs of aout+ and aoutC are in a high impedance state. the electrical driving capability of the aoutC pin and aout+ pin is 1.3 v maximum. the output load resistor has a minimum value of 1.2 k w . if an output amplitude less than 1.3 v is allowed, these outputs can drive a load resistance less than that described above. for more details, refer to single power supply pcm codec application note. v dd power supply for +3.0 v to +3.8 v. (typically 3.3 v) pcmin pcm signal input. a serial pcm signal input to this pin is converted to an analog signal in synchronization with the rsync signal and bclock signal. the data rate of the pcm signal is equal to the frequency of the bclock signal. the pcm signal is shifted at a falling edge of the bclock signal and latched into the internal register when shifted by eight bits. the start of the pcm data (msd) is identified at the rising edge of rsync. bclock shift clock signal input for the pcmin and pcmout signal. the frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048, or 200 khz. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.
? semiconductor msm7541/7542 6/20 rsync receive synchronizing signal input. eight required bits are selected from serial pcm signals on the pcmin pin by the receive synchronizing signal. signals in the receive section are synchronized by this synchronizing signal. this signal must be synchronized in phase with the bclock. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics which are mainly the frequency characteristics of the receive section. however, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 khz 2 khz, but the electrical characteristics in this specification are not guaranteed. xsync transmit synchronizing signal input. the pcm output signal from the pcmout pin is output in synchronization with this transmit synchronizing signal. this synchronizing signal triggers the pll and synchronizes all timing signals of the transmit section. this synchronizing signal must be synchronized in phase with bclock. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics which are mainly the frequency characteristics of the transmit section. however, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 khz 2 khz, but the electrical characteristics in this specification are not guaranteed. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. tmc control signal input for mode selection. this pin select the normal operating mode or the analog loop-back mode. in the analog loop-back mode, the receive filter output is connected to the transmit filter input and the digital signal input to the pcmin pin is converted from a digital to an analog signal (d/ a conversion). next, the analog signal is converted to a digital signal (a/d conversion) through the receive filter and transmit filter. the result is output to the pcmout pin. when in the analog loop-back mode, the vfro pin outputs the sg level. (signal ground) tmc input < 0.16 v dd > 0.45 v dd mode normal operation analog loop-back
? semiconductor msm7541/7542 7/20 dg ground for the digital signal circuits. this ground is separate from the analog signal ground. the dg pin must be connected to the ag pin on the printed circuit board to make a common analog ground. pdn power down control signal. a logic "0" level drives both transmit and receive circuits to a power down state. pcmout pcm signal output. the pcm output signal is output from msd in a sequential order, synchronizing with the rising edge of the bclock signal. msd may be output at the rising edge of the xsync signal, based on the timing between bclock and xsync. this pin is in a high impedance state except during 8-bit pcm output. it is also in a high impedance state during power saving or power down modes. a pull-up resistor must be connected to this pin because its output is configured as an open drain. this device is compatible with the itu-t recommendation on coding law and output coding format. the MSM7542(a-law) outputs the character signal, inverting the even bits. input/output level +full scale +0 C0 Cfull scale pcmin/pcmout msm7541 ( m -law) msd 1000 0000 1111 1111 0111 1111 0000 0000 MSM7542 (a-law) msd 1010 1010 1101 0101 0101 0101 0010 1010
? semiconductor msm7541/7542 8/20 sg signal ground voltage output. the output voltage is 1/2 of the power supply voltage. the output drive current capability is 200 m a. this pin provides the sg level for codec peripherals. this output voltage level is undefined during power saving or power down modes. sgc used to generate the signal ground voltage level by connecting a bypass capacitor. connect a 0.1 m f capacitor with excellent high frequency characteristics between the ag pin and the sgc pin.
? semiconductor msm7541/7542 9/20 absolute maximum ratings parameter power supply voltage analog input voltage digital input voltage storage temperature symbol v dd v ain v din t stg condition rating 0 to 7 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C55 to +150 unit v v v c recommended operating conditions parameter symbol power supply voltage analog input voltage digital input high voltage digital input low voltage clock frequency sync pulse frequency clock duty ratio digital input rise time digital input fall time transmit sync pulse setting time receive sync pulse setting time sync pulse width pcmin set-up time pcmin hold time digital output load analog input allowable dc offset allowable jitter width v dd v ain v ih v il f c f s d c t ir t if t xs t ws t ds t dh r dl v off t sx t rs t sr condition connect ainC and gsx xsync, rsync, bclock, pcmin, pdn, tmc bclock xsync, rsync bclock xsync, rsync, bclock, pcmin, pdn, tmc bclock ? xsync, see timing diagram xsync, rsync pull-up resistor transmit gain stage, gain = 10 xsync ? bclock, see timing diagram bclock ? rsync, see timing diagram rsync ? bclock, see timing diagram transmit gain stage, gain = 1 xsync, rsync, bclock min. typ. max. unit 3.0 0.45 v dd 0 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 6.0 40 100 1 bclk 100 100 0.5 C10 100 100 100 C100 3.3 8.0 50 3.8 1.4 v dd 0.16 v dd 10.0 60 50 50 100 +10 +100 500 100 v v pp v v khz % ns ns ns m s ns ns k w mv ns ns ns mv ns pf khz c dl voltage must be fixed operating temperature ta c C30 +25 +85
? semiconductor msm7541/7542 10/20 electrical characteristics dc and digital interface characteristics parameter power supply current input high voltage input low voltage high level input leakage current low level input leakage current digital output low voltage digital output leakage current input capacitance symbol i dd1 i dd4 i dd2 i dd3 v ih v il i ih i il v ol i o condition operating mode power-save mode, pdn = 1, xsync or bclock ? off power-down mode, pdn = 0 pull-up resistance > 500 w min. 0.45 v dd 0.0 0.0 typ. 10.0 7.0 0.3 5 0.2 max. 12.0 9.0 1.0 50 v dd 0.16 v dd 2.0 0.5 0.4 10 unit ma ma m a v v m a m a v m a v dd = 3.8 v v dd = 3.3 v c in 5pf (v dd = 3.0 v to 3.8 v, ta = C30c to +85c) ma
? semiconductor msm7541/7542 11/20 transmit analog interface characteristics receive analog interface characteristics input resistance output load resistance output load capacitance output amplitude offset voltage r inx r lgx c lgx v ogx v osgx ain+, ainC gain = 1 10 20 C0.7 C20 50 +0.7 +20 m w k w pf v mv gsx with respect to sg parameter symbol condition min. typ. max. unit (v dd = 3.0 v to 3.8 v, ta = C30c to +85c) input resistance output load resistance output load capacitance r inpw r lvf r lao c lvf c lao pwi 10 20 1.2 100 50 m w k w k w pf pf vfro with respect to sg output amplitude offset voltage v ovf v oao v osvf v osao C1.0 C1.3 C100 C100 +1.0 +1.3 +100 +100 v v mv mv vfro, r l = 20 k w with respect to sg aout+, aoutC (each) with respect to sg vfro aout+, aoutC aout+, aoutC, r l = 1.2 k w with respect to sg vfro with respect to sg aout+, aoutC, gain = 1 with respect to sg parameter symbol condition min. typ. max. unit (v dd = 3.0 v to 3.8 v, ta = C30c to +85c)
? semiconductor msm7541/7542 12/20 ac characteristics condition (v dd = 3.0 v to 3.8 v, ta = C30c to +85c) parameter symbol min. typ. max. unit transmit frequency response loss t1 level (dbm0) 60 20 26 db freq. (hz) loss t2 300 C0.15 +0.1 +0.20 db loss t3 1020 reference db 0 loss t4 2020 C0.15 +0.20 db loss t5 3000 C0.15 +0.20 db loss t6 3400 0 0.80 db receive frequency response loss r1 300 C0.15 +0.20 db loss r2 1020 reference db loss r3 2020 C0.15 +0.20 db 0 loss r4 3000 C0.15 +0.20 db loss r5 3400 0.0 0.80 db sd t1 35 43 3 sd t2 35 42 0 sd t3 35 39 C30 transmit signal to distortion ratio 1020 db sd t4 28 30.5 C40 *1 sd t5 23 25 C45 sd r1 36 43 3 sd r2 36 41 0 sd r3 36 41 C30 receive signal to distortion ratio 1020 db sd r4 30 33 C40 *1 sd r5 24 27 C45 transmit gain tracking gt t1 C0.2 0 +0.2 gt t2 reference gt t3 1020 C0.2 C0.02 +0.2 db C40 gt t4 C0.5 +0.2 +0.5 gt t5 C1.2 +0.4 +1.2 3 C10 C50 C55 receive gain tracking gt r1 C0.2 0 +0.2 gt r2 reference gt r3 1020 C0.2 C0.06 +0.2 db gt r4 C1.0 C0.10 +1.0 gt r5 C1.5 C0.20 +1.5 C40 3 C10 C50 C55 *1 psophometric filter is used
? semiconductor msm7541/7542 13/20 ac characteristics (continued) absolute level (initial difference) nidle t C70 C68 dbmop nidle r C76 av t 0.338 0.35 0.362 av r 0.483 0.50 0.518 vrms 1020 absolute delay av tt C0.2 +0.2 0 av rt C0.2 +0.2 td 1020 0.60 ms 0 a to a bclock = 64 khz transmit group delay tgd t1 0.19 0.75 tgd t2 0.11 0.35 tgd t3 0.02 0.125 0 tgd t4 0.05 0.125 ms *4 0.07 tgd t5 0.75 receive group delay 0.00 0.75 0.00 0.00 0.125 ms 0 0.09 0.125 0.12 0.75 C74 idle channel noise ain = sg *1 *2 *1 db db v dd = 3.3 v ta = 25c v dd = +3 to 3.8 v ta = C30 to +85c absolute level (deviation of temperature and power) *3 500 600 1000 2600 2800 crosstalk attenuation cr t 7585 cr r 70 1020 db 0 trans ? recv recv ? trans tgd r1 tgd r2 tgd r3 tgd r4 tgd r5 500 600 1000 2600 2800 *4 65 0.35 condition (v dd = 3.0 v to 3.8 v, ta = C30c to +85c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz) *3 *1 psophometric filter is used *2 input "0" code to pcmin *3 avr is defined at vfro output *4 minimum value of the group delay distortion
? semiconductor msm7541/7542 14/20 ac characteristics (continued) dis 4.6 khz to 30 32 db digital output delay time t sd 50 200 t xd1 50 200 t xd2 50 200 t xd3 50 200 ns discrimination 0 0 to 4000 hz c l = 100 pf + 1 lsttl s 300 to C37.5 C35 dbmo out-of-band spurious 0 4.6 khz to imd fa = 470 C52 C35 dbmo intermodulation distortion C4 2fa C fb 1020 C1.0 +1.0 db d-to-d mode gain 0 tmc = 1 pcmin to pcmout psr t 0 to 30db power supply noise rejection ratio 50 mv pp *1 psr r 72 khz 3400 fb = 320 50 khz 100 khz condition (v dd = 3.0 v to 3.8 v, ta = C30c to +85c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz) *1 the measurement under idle channel noise
? semiconductor msm7541/7542 15/20 timing diagram pcm data input/output timing bclock 12345678910 xsync pcmout d2 d3 d4 d5 d6 d7 d8 msd t xs t sx t ws t sd t xd1 t xd2 t xd3 bclock 12345678910 rsync pcmin d2 d3 d4 d5 d6 d7 msd t rs t sr t ws t ds t dh d8 transmit timing receive timing 11 when t xs 1/2 ? fc, the delay of the msd bit is defined as t xd1 . when t sx 1/2 ? fc, the delay of the msd bit is defined as t sd . 11
? semiconductor msm7541/7542 16/20 application circuit pcmout xsync ainC gsx ain+ 0.1 m f pcm signal output 8 khz sync signal input bclock input pcm data input power down control input analog interface digital interface 0.1 m f 51 k w 1 m f 10 m f + msm7541/7542 sg rsync bclock pcmin +3.3 v pdn dg aoutC pwi vfro sgc ag v dd 0 v +3.3 v 51 k w analog input analog output analog loop-back control input tmc 0 to 10 w frequency characteristics adjustment circuit ainC transmit frequency characteristic adjustment determined with c1, c2, r1, r2. receive frequency characteristic adjustment determined with c3, c4, r3, r4. receiver impedance to 1.2 k w + 55 nf gsx ain+ sg aout+ aoutC pwi vfro r2 c2 r4 c4 r1 c1 m r3 c3 microphone amp
? semiconductor msm7541/7542 17/20 recommendations for actual design ? to assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. ? connect the ag pin and the dg pin each other as close as possible. connect to the system ground with low impedance. ? mount the device directly on the board when mounted on pcbs. do not use ic sockets. if an ic socket is unavoidable, use the short lead type socket. ? when mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. ? keep the voltage on the v dd pin not lower than C0.3 v even instantaneously to avoid latch- up phenomenon when turning the power on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
? semiconductor msm7541/7542 18/20 (unit : mm) package dimensions dip20-p-300-2.54-s1 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.49 typ.
? semiconductor msm7541/7542 19/20 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sop24-p-430-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.58 typ. mirror finish
? semiconductor msm7541/7542 20/20 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 26/20-p-300-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.38 typ. mirror finish

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